ST72561AR7-Auto datasheet(298/324 Pages) STMICROELECTRONICS

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Electrical characteristics

ST72561-Auto

298/324

Doc ID 12370 Rev 8

Figure 142. RAIN max vs fADC with CAIN = 0pF

CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus

the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this,

fADC should be reduced.

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10k

Ω). Data based on characterization results, not tested in production.

RAIN

External input impedance

see

Figure 142

and

Figure 143

CAIN

External capacitor on analog

input

fAIN

Variation frequency of analog

input signal

Ilkg

Negative input leakage current

on robust analog pins (refer to

Table 3)

VIN < VSS, | IIN | < 400µA

on adjacent robust

analog pin

µA

CADC

Internal sample and hold

capacitor

6pF

tCONV

Conversion time

fADC =4 MHz

3.5

µs

1/fADC

IADC

Analog part

Sunk on VDDA

3.6

Digital part

Sunk on VDD

0.2

Data based on characterization results, not tested in production.

When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

Table 122.

ADC characteristics (continued)

Symbol

Parameter

Conditions

Min(1)

Typ

Max(1)

Unit

010

CPARASITIC (pF)

4 MHz

2 MHz

1 MHz

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