ST72561J4-Auto datasheet(248/324 Pages) STMICROELECTRONICS

248 / 324 page

beCAN controller (beCAN)

ST72561-Auto

248/324

Doc ID 12370 Rev 8

17.8.3

Mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to

Message storage for detailed register mapping.

Transmit and receive mailboxes have the same registers except:

●

MCSR register in a transmit mailbox is replaced by MFMI register in a receive mailbox.

●

A receive mailbox is always write protected.

●

A transmit mailbox is write enable only while empty, corresponding TME bit in the

CTPR register set.

Mailbox control status register (MCSR)

Read/ write

Reset value: 0000 0000 (00h)

Bits 7:6 = reserved. Forced to 0 by hardware.

Bit 5 = TERR Transmission Error

Read

This bit is updated by hardware after each transmission attempt.

0: the previous transmission was successful

1: the previous transmission failed due to an error

Bit 4 = ALST Arbitration Lost

Read

This bit is updated by hardware after each transmission attempt.

0: the previous transmission was successful

1: the previous transmission failed due to an arbitration lost

Bit 3 = TXOK Transmission OK

Read

The hardware updates this bit after each transmission attempt.

0: the previous transmission failed

1: the previous transmission was successful

Note:

This bit has the same value as the corresponding TXOKx bit in the CTSR register.

Bit 2 = RQCP Request Completed

Read/ clear

Set by hardware when the last request (transmit or abort) has been performed.

Cleared by software writing a “1” or by hardware on transmission request.

Note:

This bit has the same value as the corresponding RQCPx bit of the CTSR register.

Clearing this bit clears all the status bits (TXOK, ALST and TERR) in the MCSR register and

the RQCP and TXOK bits in the CTSR register.

Bit 1 = ABRQ Abort Request for Mailbox

Read/ set

Set by software to abort the transmission request for the corresponding mailbox.

TERR

ALST

TXOK

RQCP

ABRQ

TXRQ

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