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ST72361AR4-Auto bảng dữ liệu(PDF) 252 Page - STMicroelectronics

tên linh kiện ST72361AR4-Auto
Giải thích chi tiết về linh kiện  Clock, reset and supply management
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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ST72361AR4-Auto bảng dữ liệu(HTML) 252 Page - STMicroelectronics

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Electrical characteristics
ST72361xx-Auto
252/279
Doc ID 12468 Rev 3
Figure 118. SPI master timing diagram
1.
Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
19.13
10-bit ADC characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
SS INPUT
CPHA = 0
MOSI OUTPUT
MISO INPUT
CPHA = 0
CPHA = 1
CPHA = 1
tc(SCK)
tw(SCKH)
tw(SCKL)
th(MI)
tsu(MI)
MSB IN
MSB OUT
BIT6 IN
BIT6 OUT
LSB OUT
LSB IN
See note 2
See note 2
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
tr(SCK)
tf(SCK)
th(MO)
tv(MO)
Table 113.
ADC characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
fADC
ADC clock frequency
0.4
4
MHz
VAIN
Conversion voltage range(2)
VSSA
VDDA
V
RAIN
External input impedance
see
Figure 142
and
Figure 143
k
CAIN
External capacitor on analog
input
pF
fAIN
Variation frequency of analog
input signal
Hz
Ilkg
Negative input leakage current
on robust analog pins (refer to
Table 3)
VIN VSS, | IIN | < 400µA
on adjacent robust
analog pin
56
µA
CADC
Internal sample and hold
capacitor
6pF
tCONV
Conversion time
fADC =4 MHz
3.5
µs
14
1/fADC
IADC
Analog part
Sunk on VDDA
2)
3.6
mA
Digital part
Sunk on VDD
0.2



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