ST72361AR4-Auto datasheet(188/279 Pages) STMICROELECTRONICS

tên linh kiện	ST72361AR4-Auto

Giải thích chi tiết về linh kiện	Clock, reset and supply management

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LINSCI serial communication interface (LIN master/slave)

ST72361xx-Auto

188/279

Doc ID 12468 Rev 3

15.10.5

LIN divider registers

LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is

accessible at the address of the SCIBRR register and the LPFR register is accessible at the

address of the SCIETPR register.

15.10.6

LIN prescaler register (LPR)

Read/ write

Reset value: 0000 0000 (00h)

LPR[7:0] LIN Prescaler (mantissa of LDIV)

These 8 bits define the value of the mantissa of the LIN Divider (LDIV):

Caution:

LPR and LPFR registers have different meanings when reading or writing to them.

Consequently bit manipulation instructions (BRES or BSET) should never be used to modify

the LPR[7:0] bits, or the LPFR[3:0] bits.

15.10.7

LIN prescaler fraction register (LPFR)

Read/ write

Reset value: 0000 0000 (00h)

Bits 7:4 = Reserved.

Bits 3:0 = LPFR[3:0] Fraction of LDIV

These 4 bits define the fraction of the LIN Divider (LDIV):

LPR7

LPR6

LPR5

LPR4

LPR3

LPR2

LPR1

LPR0

Table 67.

LDIV mantissa

LPR[7:0]

Rounded mantissa (LDIV)

00h

SCI clock disabled

01h

...

FEh

254

FFh

255

LPFR3

LPFR2

LPFR1

LPFR0

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