ST72361AR4-Auto datasheet(167/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

167/279

The SCI interrupt events are connected to the same interrupt vector (see Interrupts

chapter).

These events generate an interrupt if the corresponding Enable Control Bit is set and the

interrupt mask in the CC register is reset (RIM instruction).

15.8

SCI mode register description

15.8.1

Status register (SCISR)

Read only

Reset value: 1100 0000 (C0h)

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the TDR register has been transferred into

the shift register. An interrupt is generated if the TIE = 1 in the SCICR2 register. It is cleared

by a software sequence (an access to the SCISR register followed by a write to the SCIDR

0: data is not transferred to the shift register

1: data is transferred to the shift register

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a character containing Data is complete.

An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register followed by a write to the SCIDR register).

0: transmission is not complete

1: transmission is complete

Note:

TC is not set after the transmission of a Preamble or a Break.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the RDR register has been transferred to the

SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a

software sequence (an access to the SCISR register followed by a read to the SCIDR

0: data is not received

1: received data is ready to be read

Bit 4 = IDLE Idle line detected.

This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the

ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the

SCISR register followed by a read to the SCIDR register).

0: no Idle Line is detected

1: idle Line is detected

Note:

The IDLE bit will not be set again until the RDRF bit has been set itself (that is, a new idle

line occurs).

Bit 3 = OR Overrun error

TDRE

RDRF

IDLE

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