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ST72344S2 bảng dữ liệu(PDF) 165 Page - STMicroelectronics

tên linh kiện ST72344S2
Giải thích chi tiết về linh kiện  SCI asynchronous serial interface
PDF  247 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72344S2 bảng dữ liệu(HTML) 165 Page - STMicroelectronics

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ST72344xx, ST2345xx
On-chip peripherals
Doc ID 12321 Rev 6
165/247
I2C data register (DR)
Reset value: 0000 0000 (00h)
Bits 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or transmitted on the bus.
●
Transmitter mode: byte transmission start automatically when the software writes in the
DR register.
●
Receiver mode: the first data byte is received automatically in the DR register using the
least significant bit of the address.
Then, the following data bytes are received one by one after reading the DR register.
I2C own address register (OAR1)
Reset value: 0000 0000 (00h)
7-bit addressing mode
Bits 7:1 = ADD[7:1] Interface address.
These bits define the I2C bus address of the interface. They are not cleared when the
interface is disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when
the interface is disabled (PE=0).
Note:
Address 01h is always ignored.
10-bit addressing mode
Bit 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I2C bus address of the interface. They are not
cleared when the interface is disabled (PE=0).
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read / Write
7
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read / Write



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