ST72344S2 datasheet(152/247 Pages) STMICROELECTRONICS

152 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

152/247

Doc ID 12321 Rev 6

When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs.

In this case, the value of the external pull-up resistor used depends on the application.

When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.

Figure 68.

I2C interface block diagram

11.6.4

Functional description

Refer to the CR, SR1 and SR2 registers in Section 11.6.7. for the bit definitions.

By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it

initiates a transmit or receive sequence.

First the interface frequency must be configured using the FRi bits in the OAR2 register.

Slave mode

As soon as a start condition is detected, the address is received from the SDA line and sent

to the shift register; then it is compared with the address of the interface or the General Call

address (if selected by software).

Note:

In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and

the two most significant bits of the address.

Header matched (10-bit mode only): the interface generates an acknowledge pulse if the

ACK bit is set.

Data register (DR)

Data shift register

Comparator

Own address register 1 (OAR1)

Clock control register (CCR)

Status register 1 (SR1)

Control register (CR)

Control logic

Status register 2 (SR2)

Interrupt

Clock control

Data control

SCL or SCLI

SDA or SDAI

Own address register 2 (OAR2)

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