ST72344S2 datasheet(115/247 Pages) STMICROELECTRONICS

115 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

115/247

11.4

Serial peripheral interface (SPI)

11.4.1

Introduction

The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication

with external devices. An SPI system may consist of a master and one or more slaves, or a

system in which devices may be either masters or slaves.

11.4.2

Main features

●

Full-duplex synchronous transfers (on three lines)

●

Simplex synchronous transfers (on two lines)

●

Master or slave operation

●

6 master mode frequencies (fCPU/4 max.)

●

fCPU/2 max. slave mode frequency (see the note)

●

SS Management by software or hardware

●

Programmable clock polarity and phase

●

End-of-transfer interrupt flag

●

Write collision, master mode fault and Overrun flags

Note:

In slave mode, continuous transmission is not possible at maximum frequency due to the

software overhead for clearing status flags and to initiate the next transmission sequence.

11.4.3

General description

Figure 56 on page 116 shows the serial peripheral interface (SPI) block diagram. There are

three registers:

●

SPI Control Register (SPICR)

●

SPI Control/Status Register (SPICSR)

●

SPI Data Register (SPIDR)

The SPI is connected to external devices through four pins:

●

MISO: Master In / Slave Out data

●

MOSI: Master Out / Slave In data

●

SCK: Serial Clock out by SPI masters and input by SPI slaves

●

SS: Slave select:

This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves

individually and to avoid contention on the data lines. Slave SS inputs can be driven by

standard I/O ports on the master Device.

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