ST7LITE49K2 datasheet(168/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

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SPI control/status register (SPICSR)

Reset Value: 0000 0000 (00h)

Bit 7 = SPIF Serial peripheral data transfer flag (Read only).

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared.

1: Data transfer between the device and an external device has been completed.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

Bit 6 = WCOL Write collision status (Read only).

This bit is set by hardware when a write to the SPIDR register is done during a transmit

sequence. It is cleared by a software sequence (see Figure 75).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = OVR SPI overrun error (Read only).

This bit is set by hardware when the byte currently being received in the shift register is

ready to be transferred into the SPIDR register while SPIF = 1 (See Section Overrun

condition (OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR

bit is cleared by software reading the SPICSR register.

0: No overrun error

1: Overrun error detected

Bit 4 = MODF Mode fault flag (Read only).

This bit is set by hardware when the SS pin is pulled low in master mode (see Section

Master mode fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the

SPICR register. This bit is cleared by a software sequence (An access to the SPICSR

0: No master mode fault detected

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD SPI output disable.

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI output (MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE = 1)

1: SPI output disabled

SPIF

WCOL

OVR

MODF

SOD

SSM

SSI

Read / Write (some bits Read only)

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