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SPC56EL54x bảng dữ liệu(PDF) 136 Page - STMicroelectronics

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SPC56EL54x bảng dữ liệu(HTML) 136 Page - STMicroelectronics

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Electrical characteristics
SPC56ELx, SPC564Lx
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DocID15457 Rev 12
3.21.2
WKUP/NMI timing
3.21.3
IEEE 1149.1 JTAG interface timing
2. CL includes device and package capacitance (CPKG < 5 pF).
Table 37. WKUP/NMI glitch filter
No.
Symbol
Parameter
Min
Typ
Max
Unit
1WFNMI
D NMI pulse width that is rejected
—
—
45
ns
2WNFNMI
D NMI pulse width that is passed
205
—
—
ns
Table 38. JTAG pin AC electrical characteristics
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1tJCYC
D TCK cycle time
—
62.5
—
ns
2tJDC
D TCK clock pulse width (measured at VDDE/2)
—
40
60
%
3tTCKRISE
D TCK rise and fall times (40%–70%)
—
—
3
ns
4
tTMSS,
tTDIS
D TMS, TDI data setup time
—
5
—
ns
5
tTMSH,
tTDIH
D TMS, TDI data hold time
—
25
—
ns
6tTDOV
D TCK low to TDO data valid
—
—
20
ns
7tTDOI
D TCK low to TDO data invalid
—
0
—
ns
8tTDOHZ
D TCK low to TDO high impedance
—
—
20
ns
11
tBSDV
D TCK falling edge to output valid
—
—
50
ns
12
tBSDVZ
D TCK falling edge to output valid out of high impedance
—
—
50
ns
13
tBSDHZ
D TCK falling edge to output high impedance
—
—
50
ns
14
tBSDST
D Boundary scan input valid to TCK rising edge
—
50
—
ns
15
tBSDHT
D TCK rising edge to boundary scan input invalid
—
50
—
ns



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