ENICSF2811PBKA datasheet(139/172 Pages) TI1

139 / 172 page

Lead 1

Active

Trail

XCLKOUT = XTIMCLK

XCLKOUT = 1/2 XTIMCLK

XA[0:18]

XD[0:15]

d(XCOHL-XWEH)

d(XCOHL-XZCSH)

d(XCOH-XA)

WS (Async)

XZCS0AND1 XZCS2

XZCS6AND7

XRD

XWE

XR/W

d(XCOH-XZCSL)

d(XCOH-XRNWL)

d(XCOHL-XRNWH)

en(XD)XWEL

h(XD)XWEH

h(XRDYasynchL)

DOUT

dis(XD)XRNW

h(XRDYasynchH)XZCSH

See Note (E)

See Note (D)

su(XRDYasynchL)XCOHL

su(XRDYasynchH)XCOHL

d(XWEL-XD)

d(XCOHL-XWEL)

See

Notes (A)

and (B)

See Note (C)

= Don’t care. Signal can be high or low during this time.

Legend:

e(XRDYasynchH)

XREADY(Asynch)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an

alignment cycle before an access to meet this requirement.

During alignment cycles, all signals will transition to their inactive state.

During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes

alignment cycles.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL

where n is the sample number (n = 1, 2, 3 and so forth).

Reference for the first sample is with respect to this point

E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)

Figure 6-36. Write With Asynchronous XREADY Access

XTIMING register parameters used for this example:

XRDLEAD

XRDACTIVE

XRDTRAIL

USEREADY

X2TIMING

XWRLEAD

XWRACTIVE

XWRTRAIL

READYMODE

1 = XREADY

N/A(1)

≥ 1

(Async)

(1)

N/A = “Don’t care” for this example

Electrical Specifications

139

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