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ENICSF2811PBKA bảng dữ liệu(PDF) 121 Page - Texas Instruments

tên linh kiện ENICSF2811PBKA
Giải thích chi tiết về linh kiện  Digital Signal Processors
PDF  172 Pages
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ENICSF2811PBKA bảng dữ liệu(HTML) 121 Page - Texas Instruments

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11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Data Valid
Master Out Data Is Valid
SPISTE
(A)
1
2
3
6
10
7
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
A.
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays
active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-27. SPI Master External Timing (Clock Phase = 1)
Copyright © 2001–2012, Texas Instruments Incorporated
Electrical Specifications
121
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812



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