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DDR_CLK
1
TMS320C6424
www.ti.com
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
6.9.4.1
DDR2 Memory Controller Electrical Data/Timing
The Implementing DDR2 PCB Layout on the TMS320C6421/4 DMSoC Application Report (literature
number SPRAAL7) specifies a complete DDR2 interface solution for the C6424 as well as a list of
compatible DDR2 devices. TI has performed the simulation and system characterization to ensure all
DDR2 interface timings in this solution are met.
TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout
on the TMS320C6421/4 DMSoC Application Report (literature number SPRAAL7).
Table 6-27. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller(1) (2)(see Figure 6-18)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
PARAMETER
UNIT
MIN
MAX
1
tc(DDR_CLK)
Cycle time, DDR_CLK
6
8
ns
(1)
DDR_CLK cycle time = 2 x PLL2 _SYSCLK1 cycle time.
(2)
The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range.
Figure 6-18. DDR2 Memory Controller Clock Timing
Copyright © 2007–2009, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
179
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Product Folder Link(s): TMS320C6424



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