PC97307 datasheet(204/218 Pages) NSC

tên linh kiện	PC97307

Giải thích chi tiết về linh kiện	PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

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Device Description

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13.3.12 Reset Timing

TABLE 13-47. Reset Timing

Note:

In PC-AT mode, the DRQ and IRQ signals of the FDC are in TRI-STATE after time tSRC.

FIGURE 13-17. Reset Timing

13.3.13 Write Data Timing

TABLE 13-48. Write Data Timing

TABLE 13-49. Write Data Timing – Minimum tWDW Values

FIGURE 13-18. Write Data Timing

a. The software reset pulse width is 100 nsec.

b. Not tested. Guaranteed by design.

a. Not tested. Guaranteed by design.

a. tICP is the internal clock period defined in Table 13-36.

Symbol

Parameter

Min

Max

Unit

tRW

Reset Width a

100

µsec

tSRC

Reset to Control Inactive b

300

nsec

Symbol

Parameter

Min

Max

Unit

tHDH

HDSEL Hold from WGATE Inactivea

750

µsec

tHDS

HDSEL Setup to WGATE Activea

100

µsec

tWDW

Write Data Pulse Width

Table 13-49

Data Rate

tDRP

tWDW

tWDW Value

Unit

1 Mbps

1000

2 x tICP

250

nsec

500 Kbps

2000

2 x tICP

250

nsec

300 Kbps

3333

2 x tICP

375

nsec

250 Kbps

4000

2 x tICP

500

nsec

tRW

tSRC

DRQ,

INT,

WGATE (Note)

tHDS

tHDH

tWDW

HDSEL

WGATE

WDATA

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