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STM32F756VG bảng dữ liệu(PDF) 102 Page - STMicroelectronics

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STM32F756VG bảng dữ liệu(HTML) 102 Page - STMicroelectronics

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Electrical characteristics
STM32F756xx
102/228
DocID027589 Rev 4
5.3.3
Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up / power-down (regulator ON)
5.3.4
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
5.3.5
Reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
Table 19. VCAP1/VCAP2 operating conditions(1)
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol
Parameter
Conditions
CEXT
Capacitance of external capacitor
2.2 µF
ESR
ESR of external capacitor
< 2
Ω
Symbol
Parameter
Min
Max
Unit
tVDD
VDD rise time rate
20
∞
µs/V
VDD fall time rate
20
∞
Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Symbol
Parameter
Conditions
Min
Max
Unit
tVDD
VDD rise time rate
Power-up
20
∞
µs/V
VDD fall time rate
Power-down
20
∞
tVCAP
VCAP_1 and VCAP_2 rise time rate Power-up
20
∞
VCAP_1 and VCAP_2 fall time rate
Power-down
20
∞



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