ST72774 datasheet(105/144 Pages) STMICROELECTRONICS

105 / 144 page

ST72774/ST727754/ST72734

105/144

DDC INTERFACE (Cont’d)

Write Operation

Once the DDC1/2B Interface has acknowledged a

write transfer request, i.e. a Device Address with

RW=0, it waits for a data address. When the latter

is received, it is acknowledged and loaded into the

ALR.

Then, the master may send any number of data

bytes that are all acknowledged by the DDC1/2B

Interface. The data bytes are written in RAM if the

WP bit=0 in the DCR register, otherwise the RAM

location is not modified.

In any case, all write operations are performed

in RAM and therefore do not delay DDC

transfers,

although

concurrent

software

execution is halted for 2 cycles.

After each byte is transferred, the internal address

counter is automatically incremented.

If the counter is pointing to the top of the structure,

it rolls over to the bottom since the incrementation

is performed only on the 7 or 8 LSB’s of the pointer

depending on the selected data structure size. In

other words, ALR rolls over from FFh to 00h for

Device

Addresses

A2h/A3h

and

A6h/A7h.

Otherwise, it rolls over from 7Fh to 00h or from FFh

to 80h depending on the MSB of the last data

address received.

Then after that last byte has been effectively

written in RAM, the EDF flag is set and an interrupt

is generated if EDE is set.

The

transfer

terminated

the

master

generating a STOP condition.

Figure 65. Write sequence

Read Operations

All read operations consist of retrieving the data

pointed to by an internal address counter which is

initialized by a dummy write and incremented by

any read. The DDC1/2B Interface always waits for

an acknowledge during the 9th bit-time. If the

master does not pull the SDA line low during this

bit-time, the DDC1/2B Interface ends the transfer

and switches to a stand-by state.

– Current address read: After generating a

START condition the master sends a read device

address (RW = 1). The DDC1/2B Interface ac-

knowledges this and outputs the data byte point-

ed to by the internal address pointer which is

subsequently incremented. The master must

NOT acknowledge this byte and must terminate

the transfer with a STOP condition.

– Random address read: The master performs a

dummy write to load the data address into the

ALR. Then the master sends a RESTART condi-

tion followed by a read Device Address (RW=1).

– Sequential address read: This mode is similar

to the current and random address reads, except

that the master DOES acknowledge the data

byte for the DDC1/2B Interface to output the next

byte in sequence. To terminate the read opera-

tion the master must NOT acknowledge the last

data byte and must generate a STOP condition.

The data output are from consecutive memory

addresses. The internal address counter is incre-

mented automatically after each byte. If the

counter is pointing to the top of the structure, it

rolls over to the bottom since the incrementation

is performed only on the 7 or 8 LSB’s of the

counter depending on the selected data structure

size.

DATA ADDR.

DATA IN 1

DATA IN 2

DATA IN n

DEV ADDR

SDA

XXXXh

ADDR

ADDR + n -1

Addr.

Pointer

ADDR + 1

ADDR + n

ST72774 bảng dữ liệu(PDF) 105 Page - STMicroelectronics

ST72774 bảng dữ liệu(HTML) 105 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL