OMAP3530ECUS72 datasheet(235/265 Pages) TI1

235 / 265 page

OMAP3530, OMAP3525

www.ti.com

SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013

6.7

Removable Media Interfaces

6.7.1

High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing

The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory

cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The

MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding

CRC, start/end bit, and checking for syntactical correctness.

There are three MMC interfaces on the OMAP3530/25:

•

MMC/SD/SDIO Interface 1:

–

1.8 V/3 V support

–

8 bits

•

MMC/SD/SDIO Interface 2:

–

1.8 V support

–

8 bits

–

4 bits with external transceiver allowing to support 3 V peripherals. Transceiver direction control

signals are multiplexed with the upper four data bits.

•

MMC/SD/SDIO Interface 3:

–

1.8 V support

–

8 bits

6.7.1.1

MMC/SD/SDIO in SD Identification Mode

Table 6-118 and Table 6-119 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-117. MMC/SD/SDIO Timing Conditions – SD Identification Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

SD Identification Mode

Input Conditions

Input signal rise time

Input signal fall time

Output Conditions

CLOAD

Output load capacitance

Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode(1) (2) (3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SD Identification Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

HSSD3/SD3

tsu(CMDV-CLKIH)

Setup time, mmc1_cmd valid before

1198.4

mmc1_clk rising clock edge

HSSD4/SD4

tsu(CLKIH-CMDIV)

Hold time, mmc1_cmd valid after

1249.2

mmc1_clk rising clock edge

MMC/SD/SDIO Interface 1 (3.0 V IO)

HSSD3/SD3

tsu(CMDV-CLKIH)

Setup time, mmc1_cmd valid before

1198.4

mmc1_clk rising clock edge

HSSD4/SD4

tsu(CLKIH-CMDIV)

Hold time, mmc1_cmd valid after

1249.2

mmc1_clk rising clock edge

MMC/SD/SDIO Interface 2

(1)

Timing parameters are referred to output clock specified in Table 6-119.

(2)

The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-119.

(3)

Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

235

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