PC87413 datasheet(188/257 Pages) NSC

188 / 257 page

9.0 System Wake-Up Control (SWC) (Continued)

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188

Revision1.2

9.3.11

Power On Control Register (PWONCTL)

This register controls the power-On process and the way the PC8741x device resumes operation after Power Fail. It is reset

by hardware to 87h.

Power Well:VPP

Location: All Banks, Offset 09h

Type:

Varies per bit

Bit

43210

Name

WAS

_PFAIL

LAST

_ONCTL

RESUME_MD

LEGACY

_PWBT1

1. This bit is powered from the VDD well and is reset either by VDD power-up reset or by hardware reset.

CRBAR_TOUT

Reset

00111

Bit

Type

Description

R/W1C WAS_PFAIL (Was Power Fail Status). Indicates that the device has woken up from a Power Fail

condition (VDD and VSB off). This bit is set by VSB Power-Up reset. Writing ‘1’ clears this bit; writing ‘0’

is ignored.

0: Inactive

1: Wake-up from Power Fail (default)

6RO

LAST_ONCTL (Last Value of ONCTL). This bit reﬂects the last value of the ONCTL signal when the

previous Power Fail condition (VDD and VSB off) occurred. Writing to this bit is ignored.

0: ONCTL inactive - VDD power Off (default)

1: ONCTL active - VDD power On

5-4

R/W

RESUME_MD (Resume Mode Control). These bits control the power state to which the PC8741x

device resumes after waking-up from a Power Fail condition (i.e., when VDD and VSB are off). Table 49

shows the behavior of the ONCTL and PWBTOUT signals in all four Resume modes.

R/W

LEGACY_PWBT (Legacy Power Button). This bit allows the Power button to set ONCTL to inactive

level (VDD power supply Off).

0: ACPI-compliant Power button - VDD power turned off by sleep state (written into SLP_TYPx field or

decoded from SLPS3 and SLPS5) or by a Power Button Override condition (default)

1: Legacy Power button - VDD power turned off by pressing the Power button (PWBTIN) when the VDD

power is on

2-0

R/W

CRBAR_TOUT (Crowbar Timeout Conﬁguration). This ﬁeld controls the timeout value for the

Crowbar function (the time between the activation of ONCTL and its deactivation as a result of VDD

remaining off). After the Crowbar timeout, the PC8741x device waits another second before it accepts

a new Power button event.

Bits

2 1 0

Timeout (Seconds)

0 0 0:

0.5

0 0 1:

0 1 0:

0 1 1:

1 0 0:

1 0 1:

1 1 0:

1 1 1:

20 (default)

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