PC87413 datasheet(154/257 Pages) NSC

154 / 257 page

8.0 Real-Time Clock (RTC) (Continued)

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154

Revision1.2

8.3.13

RTC Control Register A (CRA)

This register controls test selection in addition to other functions. This register cannot be written before reading bit 7 of the

CRD register.

Power Well:VPP

Location: Index 0Ah

Type:

Varies per bit

Table 37. Divider Chain Control and Test Selection

Bit

76543210

Name

Update in

Progress

Divider Chain Control

Periodic Interrupt Rate Select

Reset

00100000

Bit

Type

Description

7RO

Update in Progress. This bit is not affected by reset. It reads 0 when bit 7 of the CRB register is 1.

0: Timing registers not updated within 244

µs

1: Timing registers updated within 244

µs

6-4

R/W

Divider Chain Control. These bits control the conﬁguration of the divider chain for timing generation

(see Table 37). They are cleared to 000 as long as bit 7 of the CRD register reads 0.

3-0

R/W

Periodic Interrupt Rate Select. These bits select one of 15 output taps from the clock divider chain to

control the rate of the periodic interrupt (see Table 38 and Figure 41 on page 144). They are cleared to

000 as long as bit 7 of the CRD register reads 0.

DV2

(CRA6)

DV1

(CRA5)

DV0

(CRA4)

Conﬁguration

Oscillator Disabled

Normal Operation

011

Reserved

Divider Chain Reset

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