STM32F446RC datasheet(165/201 Pages) STMICROELECTRONICS

165 / 201 page

DocID027107 Rev 5

165/201

STM32F446xC/E

Electrical characteristics

174

NAND controller waveforms and timings

Figure 58 through Figure 61 represent synchronous waveforms, and Table 98 and Table 99

provide the corresponding timings. The results shown in this table are obtained with the

following FMC configuration:

•

COM.FSMC_SetupTime = 0x01;

•

COM.FMC_WaitSetupTime = 0x03;

•

COM.FMC_HoldSetupTime = 0x02;

•

COM.FMC_HiZSetupTime = 0x01;

•

ATT.FMC_SetupTime = 0x01;

•

ATT.FMC_WaitSetupTime = 0x03;

•

ATT.FMC_HoldSetupTime = 0x02;

•

ATT.FMC_HiZSetupTime = 0x01;

•

Bank = FMC_Bank_NAND;

•

MemoryDataWidth = FMC_MemoryDataWidth_16b;

•

ECC = FMC_ECC_Enable;

•

ECCPageSize = FMC_ECCPageSize_512Bytes;

•

TCLRSetupTime = 0;

•

TARSetupTime = 0.

In all timing tables, the THCLK is the HCLK clock period.

Table 97. Synchronous non-multiplexed PSRAM write timings(1)(2)

1. CL = 30 pF.

2. Guaranteed based on test during characterization.

Symbol

Parameter

Min

Max

Unit

tw(CLK)

FMC_CLK period

2THCLK – 1

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)

2.5

td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)

THCLK – 0.5

td(CLKL-NADVL) FMC_CLK low to FMC_NADV low

td(CLKL-NADVH) FMC_CLK low to FMC_NADV high

td(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x=16…25)

td(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x=16…25)

td(CLKL-NWEL) FMC_CLK low to FMC_NWE low

td(CLKH-NWEH) FMC_CLK high to FMC_NWE high

THCLK + 1

td(CLKL-Data)

FMC_D[15:0] valid data after FMC_CLK low

2.5

td(CLKL-NBLL) FMC_CLK low to FMC_NBL low

td(CLKH-NBLH) FMC_CLK high to FMC_NBL high

THCLK + 1.5

tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high

1.5

th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high

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