| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
STM32F446RC bảng dữ liệu(PDF) 139 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32F446RC bảng dữ liệu(HTML) 139 Page - STMicroelectronics |
|
139 / 201 page ![]() DocID027107 Rev 5 139/201 STM32F446xC/E Electrical characteristics 174 USB high speed (HS) characteristics Unless otherwise specified, the parameters given in Table 73 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 72 and VDD supply voltage conditions summarized in Table 71, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10, unless otherwise specified • Capacitive load C = 30 pF, unless otherwise specified • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Table 70. USB OTG full speed electrical characteristics(1) 1. Guaranteed by design. Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). CL = 50 pF 420 ns tf Fall time(2) CL = 50 pF 4 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage - 1.3 2.0 V ZDRV Output driver impedance(3) 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. Driving high or low 28 44 Ω Table 71. USB HS DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD USB OTG HS operating voltage 1.7 3.6 V Table 72. USB HS clock timing parameters(1) Symbol Parameter Min Typ Max Unit - fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66 MHz FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60 % DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 % tSTEADY Time to reach the steady state frequency and duty cycle after the first transition -- 1.4 ms |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |