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STM32F446ME bảng dữ liệu(PDF) 136 Page - STMicroelectronics |
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STM32F446ME bảng dữ liệu(HTML) 136 Page - STMicroelectronics |
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136 / 201 page ![]() Electrical characteristics STM32F446xC/E 136/201 DocID027107 Rev 5 SAI characteristics Unless otherwise specified, the parameters given in Table 67 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). (3) Table 67. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK SAI Main clock output - 256 x 8K 256 x Fs MHz fCK SAI clock frequency(2) Master data: 32 bits - 128 x Fs(3) MHz Slave data: 32 bits - 128 x Fs(3) tv(FS) FS valid time Master mode 2.7 V ≤ VDD ≤3.6 V -14 % Master mode 1.71 V ≤ VDD ≤3.6 V -17.5 ns th(FS) FS hold time Master mode 7 - tsu(FS) FS setup time Slave mode 1 - th(FS) FS hold time Slave mode 1 - tsu(SD_A_MR) Data input setup time Master receiver 1 - tsu(SD_B_SR) Slave receiver 1 - th(SD_A_MR) Data input hold time Master receiver 5 - th(SD_B_SR) Slave receiver 1 - tv(SD_B_ST) Data output valid time Slave trasmitter (after enable edge 2.7 V ≤ VDD ≤3.6 V -9.5 Slave transmitter (after enable edge 1.71 V ≤ VDD ≤3.6 V -16 th(SD_B_ST) Data output hold time Slave transmitter (after enable edge 6 - tv(SD_B_ST) Data output valid time Master transmitter (after enable edge 2.7 V ≤ VDD ≤3.6 V -15 Master transmitter (after enable edge 1.71 V ≤ VDD ≤3.6 V -18 th(SD_B_ST) Data output hold time Master transmitter (after enable edge 7 - 1. Guaranteed based on test during characterization. 2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency) 3. With Fs = 192 KHz |
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