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ADP1055ACPZ-R7 bảng dữ liệu(PDF) 119 Page - Analog Devices

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ADP1055ACPZ-R7 bảng dữ liệu(HTML) 119 Page - Analog Devices

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Data Sheet
ADP1055
Rev. A | Page 119 of 140
Table 207. Register 0xFE5F—SR_SETTING
Bits
Bit Name
R/W
Description
[7:4]
SR phase-in
speed
R/W
SR edges move by 5 ns every 1/2/4/8/16/32/64/128/256/384/512/640/768/832/960/1024 (total of 16).
SR outputs are always phased in during soft start, soft stop, and all mode transitions; for example, if SR
outputs enter pulse skip or are disabled, they turn on again at the phase-in speed selected by these
bits.
Bit 7
Bit 6
Bit 5
Bit 4
Multiplier
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
0
0
1
1
8
0
1
0
0
16
0
1
0
1
32
0
1
1
0
64
0
1
1
1
128
1
0
0
0
256
1
0
0
1
384
1
0
1
0
512
1
0
1
1
640
1
1
0
0
768
1
1
0
1
832
1
1
1
0
960
1
1
1
1
1024
[3:1]
SR LLM threshold
R/W
These bits set the load current limit on the CS2 ADC below which SR1 and SR2 enter the light load mode
(SR on during forward conduction only). Averaging time, debounce, and hysteresis are the same
values set in Register 0xFE4B.
Bit 3
Bit 2
Bit 1
Thresholds (LSBs)
0
0
0
0
0
0
1
4
0
1
0
8
0
1
1
12
1
0
0
16
1
0
1
20
1
1
0
24
1
1
1
28
0
Blank SR during
soft start
R/W
1 = blank SR during soft start.
Table 208. Register 0xFE60—NOMINAL_TEMP_POLE
Bits
Bit Name
R/W
Description
[7:0]
ADD_PZ
R/W
Additional pole/zero setting. A value of 0 disables ADD_PZ.
The analog frequency (in rad/sec) is located at w = ln(reg_val/256)/tSW, where tSW is the switching
period and reg_val is the contents of Register 0xFE60 and Register 0xFE61 in decimal format.
Table 209. Register 0xFE61—LOW_TEMP_POLE
Bits
Bit Name
R/W
Description
[7:0]
ADD_PZ
R/W
Additional pole/zero setting. A value of 0 disables ADD_PZ.
The analog pole frequency in rad/sec is located at w = ln(0xFE61[7:0]/256)/tSW, where tSW is the
switching period.



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