ADE7166_15 datasheet(138/152 Pages) AD

138 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 138 of

152

SPI INTERRUPT AND STATUS FLAGS

The SPI interface has several status flags that indicate the status

of the double-buffered receive and transmit registers. Figure 111

shows when the status and interrupt flags are raised. The transmit

interrupt occurs when the internal serial port shift register is loaded

with the data in the SPI/I2C transmit buffer SFR (SPI2CTx,

Address 0x9A) register. If the SPI master is in transmit

operating mode, and the SPI/I2C transmit buffer SFR (SPI2CTx,

Address 0x9A) register has not been written with new data by

the beginning of the next byte transfer, the transmit operation

stops.

When a new byte of data is received in the SPI/I2C receive

buffer SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt

flag is raised. If the data in the SPI/I2C receive buffer SFR

(SPI2CRx, Address 0x9B) is not read before new data is ready to

be loaded into the SPI/I2C receive buffer SFR (SPI2CRx,

Address 0x9B), an overflow condition has occurred. This

overflow condition, indicated by the SPIRxOF flag, forces the

new data to be discarded or overwritten if the RxOFW bit

(SPIMOD1, Address 0xE8) is set.

SPITx

TRANSMIT SHIFT REGISTER

SPITxIRQ = 1

SPITx (EMPTY)

TRANSMIT SHIFT REGISTER

STOPS TRANSFER IF TIMODE = 1

SPIRx

RECEIVE SHIFT REGISTER

SPIRxIRQ = 1

SPIRx (FULL)

RECEIVE SHIFT REGISTER

SPIRxOF = 1

Figure 111. SPI Receive and Transmit Interrupt and Status Flags

SCLK

(SPICPOL=0)

MISO

SCLK

(SPICPOL = 1)

MOSI

SPIRx1 AND

SPITx1 FLAGS

SS_b

SPIRx0 AND

SPITx0 FLAGS

SPICPHA = 1

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

MISO

MOSI

SPIRx1 AND

SPITx1 FLAGS

SPIRx0 AND

SPITx0 FLAGS

SPICPHA = 0

Figure 112. SPI Timing Configurations

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