AD7398/AD7399

Rev. C | Page 8 of 24

INPUT REGISTERS

AD7398 SERIAL INPUT REGISTER DATA FORMAT

Data is loaded in the MSB first format.

MSB

LSB

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

SA

SD

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NOTE

Bit Position B14 and Bit Position B15 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set

to Logic 1, the address decoded by Bit B12 and Bit B13 (A0 and A1) determine the DAC channel that is placed in the power shutdown state.

AD7399 SERIAL INPUT REGISTER DATA FORMAT

Data is loaded in the MSB first format.

MSB

LSB

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

SA

SD

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NOTE

Bit Position B12 and Bit Position B13 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set

to Logic 1, the address decoded by Bit B10 and Bit B11 (A0 and A1) determine the DAC channel that is placed in the power shutdown state.

Table 6. AD7398/AD7399 Address Decode Control

SA

SD

A1

A0

DAC Channel Affected

1

X

X

X

All DACs shutdown

0

1

0

0

DAC A shutdown

0

1

0

1

DAC B shutdown

0

1

1

0

DAC C shutdown

0

1

1

1

DAC D shutdown

0

0

0

0

DAC A input register decoded

0

0

0

1

DAC B input register decoded

0

0

1

0

DAC C input register decoded

0

0

1

1

DAC D input register decoded