AT80SND2CMP3B datasheet(153/242 Pages) ATMEL

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153

4341H–MP3–10/07

AT8xC51SND2C/MP3B

Table 18-12. MMINT Register

MMINT (S:E7h Read Only) – MMC Interrupt Register

Reset Value = 0000 0011b

MCBI

EORI

EOCI

EOFI

F2FI

F1FI

F2EI

F1EI

Bit Number

Bit

Mnemonic

Description

MCBI

MMC Card Busy Interrupt Flag

Set by hardware when the card enters or exits its busy state (when the busy signal is

asserted or deasserted on the data line).

Cleared when reading MMINT.

EORI

End of Response Interrupt Flag

Set by hardware at the end of response reception.

Cleared when reading MMINT.

EOCI

End of Command Interrupt Flag

Set by hardware at the end of command transmission.

Clear when reading MMINT.

EOFI

End of Frame Interrupt Flag

Set by hardware at the end of frame (stream or block) transfer.

Clear when reading MMINT.

F2FI

FIFO 2 Full Interrupt Flag

Set by hardware when second FIFO becomes full.

Cleared by hardware when second FIFO becomes empty.

F1FI

FIFO 1 Full Interrupt Flag

Set by hardware when first FIFO becomes full.

Cleared by hardware when first FIFO becomes empty.

F2EI

FIFO 2 Empty Interrupt Flag

Set by hardware when second FIFO becomes empty.

Cleared by hardware when second FIFO becomes full.

F1EI

FIFO 1 Empty Interrupt Flag

Set by hardware when first FIFO becomes empty.

Cleared by hardware when first FIFO becomes full.

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