AT90PWM2 datasheet(253/365 Pages) ATMEL

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253

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

- By setting the ADASCR (Analog to Digital Conversion on Amplified Channel Start Conversion

Request) bit in the ADCSRB register on AT90PWM2/3. Then, the ADSC bit of the ADCSRA

- By setting the ADSC (ADC Start conversion) bit in the ADCSRB register on AT90PWM2B/3B.

Until the conversion is not achieved, it is not possible to start a conversion on another channel.

In order to have a better understanding of the functioning of the amplifier synchronization, a tim-

ing diagram example is shown Figure 21-15 for AT90PWM2/3.

Figure 21-15. Amplifier synchronization timing diagram for AT90PWM2/3.

It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-

sion is started at the next amplifier clock event following the last auto trigger event selected

thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running

mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.

Only PSC sources can auto trigger the amplified conversion. In this case, the core must have a

clock synchronous with the PSC. If the PSC uses the PLL clock, the core must use the PLL/4

clock source.

Valid sample

Delta V

4th stable sample

Signal to be

measured

AMPLI_clk

(Sync Clock)

CK ADC

Amplifier Sample

Enable

Amplifier Hold

Value

PSCn_ASY

PSC

Block

Amplifier

Block

ADASCR

ADSC

ADC

ADC Result Ready

ADC

Sampling

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