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PIC18F242 bảng dữ liệu(PDF) 147 Page - Microchip Technology

tên linh kiện PIC18F242
Giải thích chi tiết về linh kiện  High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D
PDF  332 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
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PIC18F242 bảng dữ liệu(HTML) 147 Page - Microchip Technology

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© 2006 Microchip Technology Inc.
DS39564C-page 145
PIC18FXX2
15.4.4.5
Clock Synchronization and
the CKP bit
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
assert the SCL line until an external I2C master device
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set, and all other
devices on the I2C bus have de-asserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum
high
time
requirement
for
SCL
(see
Figure 15-12).
FIGURE 15-12:
CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1
DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
de-asserts clock
Master device
asserts clock



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