PIC18F242 datasheet(280/332 Pages) MICROCHIP

280 / 332 page

PIC18FXX2

DS39564C-page 278

FIGURE 22-12:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 22-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.

No.

Symbol

Characteristic

Min

Max Units Conditions

TssL2scH,

TssL2scL

↓ to SCK↓ or SCK↑ input

TCY

—ns

TscH

SCK input high time

(Slave mode)

Continuous

1.25 TCY + 30

—

71A

Single Byte

—

(Note 1)

TscL

SCK input low time

(Slave mode)

Continuous

1.25 TCY + 30

—

72A

Single Byte

—

(Note 1)

TdiV2scH,

TdiV2scL

Setup time of SDI data input to SCK edge

100

—

73A

TB2B

Last clock edge of Byte1 to the 1st clock edge of Byte2

1.5 TCY + 40

—

(Note 2)

TscH2diL,

TscL2diL

Hold time of SDI data input to SCK edge

100

—

TdoR

SDO data output rise time

PIC18FXXX

—

PIC18LFXXX

—

VDD = 2V

TdoF

SDO data output fall time

PIC18FXXX

—

PIC18LFXXX

—

VDD = 2V

TscR

SCK output rise time

(Master mode)

PIC18FXXX

—

PIC18LFXXX

—

VDD = 2V

TscF

SCK output fall time (Master mode) PIC18FXXX

—

PIC18LFXXX

—

VDD = 2V

TscH2doV,

TscL2doV

SDO data output valid after SCK

edge

PIC18FXXX

—

PIC18LFXXX

—

150

VDD = 2V

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb

LSb

bit6 - - - - - -1

MSb In

LSb In

bit6 - - - -1

Note:

Refer to Figure 22-4 for load conditions.

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