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STM32F415VG bảng dữ liệu(PDF) 153 Page - STMicroelectronics

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STM32F415VG bảng dữ liệu(HTML) 153 Page - STMicroelectronics

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STM32F415xx, STM32F417xx
Electrical characteristics
NAND controller waveforms and timings
Figure 69 through Figure 72 represent synchronous waveforms, and Table 85 and Table 86
provide the corresponding timings. The results shown in this table are obtained with the
following FSMC configuration:
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
Table 84. Switching characteristics for PC Card/CF read and write cycles
in I/O space(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NIOWR)
FSMC_NIOWR low width
8THCLK –1
-
ns
tv(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid
-
5THCLK– 1
ns
th(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid
8THCLK– 2
-
ns
td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid
-
5THCLK+ 2.5
ns
th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid
5THCLK–1.5
-
ns
td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid
-
5THCLK+ 2
ns
th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid
5THCLK– 1.5
-
ns
tw(NIORD)
FSMC_NIORD low width
8THCLK–0.5
-
ns
tsu(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high
9
-
ns
td(NIORD-D)
FSMC_D[15:0] valid after FSMC_NIORD high
0
-
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.



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