PIC18F4680ISPQTP datasheet(105/482 Pages) MICROCHIP

105 / 482 page

Preliminary

DS39625C-page 103

PIC18F2585/2680/4585/4680

EXAMPLE 6-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

6.5.2

WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

6.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. If the write operation is interrupted

by a MCLR Reset or a WDT Time-out Reset during

normal operation, the user can check the WRERR bit

and rewrite the location(s) as needed.

6.5.4

PROTECTION AGAINST SPURIOUS

WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 24.0 “Special Features of the

CPU” for more detail.

6.6

Flash Program Operation During

Code Protection

See Section 24.5 “Program Verification and Code

Protection” for details on code protection of Flash

program memory.

TABLE 6-2:

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

PROGRAM_MEMORY

BSF

EECON1, EEPGD

; point to Flash program memory

BCF

EECON1, CFGS

; access Flash program memory

BSF

EECON1, WREN

; enable write to memory

BCF

INTCON, GIE

; disable interrupts

MOVLW

55h

Required

MOVWF

EECON2

; write 55h

Sequence

MOVLW

0AAh

MOVWF

EECON2

; write 0AAh

BSF

EECON1, WR

; start program (CPU stall)

BSF

INTCON, GIE

; re-enable interrupts

BCF

EECON1, WREN

; disable write to memory

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values on

page

TBLPTRU

—

bit21

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

TBPLTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL

Program Memory Table Pointer High Byte (TBLPTR<7:0>)

TABLAT

Program Memory Table Latch

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

EECON2

EEPROM Control Register 2 (not a physical register)

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

IPR2

OSCFIP

CMIP(1)

—

EEIP

BCLIP

HLVDIP

TMR3IP

ECCP1IP(1)

PIR2

OSCFIF

CMIF(1)

—

EEIF

BCLIF

HLVDIF

TMR3IF

ECCP1IF(1)

PIE2

OSCFIE

CMIE(1)

—

EEIE

BCLIE

HLVDIE

TMR3IE

ECCP1IE(1)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

Note 1:

These bits are available in PIC18F4X8X devices and reserved in PIC18F2X8X devices.

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