PIC18F4680ISPQTP datasheet(342/482 Pages) MICROCHIP

342 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 340

Preliminary

23.15.1

INTERRUPT CODE BITS

To simplify the interrupt handling process in user firm-

ware, the ECAN module encodes a special set of bits. In

Mode 0, these bits are ICODE<3:1> in the CANSTAT

the CANSTAT register. Interrupts are internally prioritized

such that the higher priority interrupts are assigned lower

values. Once the highest priority interrupt condition has

been cleared, the code for the next highest priority inter-

rupt that is pending (if any) will be reflected by the ICODE

bits (see Table 23-5). Note that only those interrupt

sources that have their associated interrupt enable bit set

will be reflected in the ICODE bits.

In Mode 2, when a receive message interrupt occurs,

the EICODE bits will always consist of ‘10000’. User

firmware may use FIFO pointer bits to actually access

the next available buffer.

23.15.2

TRANSMIT INTERRUPT

When the transmit interrupt is enabled, an interrupt will

be generated when the associated transmit buffer

becomes empty and is ready to be loaded with a new

message. In Mode 0, there are separate interrupt

enable/disable and flag bits for each of the three dedi-

cated transmit buffers. The TXBnIF bit will be set to indi-

cate the source of the interrupt. The interrupt is cleared

by the MCU, resetting the TXBnIF bit to a ‘0’. In Mode 1

and 2, all transmit buffers share one interrupt enable/

disable bit and one flag bit. In Mode 1 and 2, TXBnIE in

PIE3 and TXBnIF in PIR3 indicate when a transmit

buffer has completed transmission of its message. TXB-

nIF, TXBnIE and TXBnIP in PIR3, PIE3 and IPR3,

respectively, are not used in Mode 1 and 2. Individual

transmit buffer interrupts can be enabled or disabled by

setting or clearing TXBIE and BIE0 register bits. When a

shared interrupt occurs, user firmware must poll the

TXREQ bit of all transmit buffers to detect the source of

interrupt.

23.15.3

RECEIVE INTERRUPT

When the receive interrupt is enabled, an interrupt will

be generated when a message has been successfully

received and loaded into the associated receive buffer.

This interrupt is activated immediately after receiving

the End-Of-Frame (EOF) field.

In Mode 0, the RXBnIF bit is set to indicate the source

of the interrupt. The interrupt is cleared by the MCU,

resetting the RXBnIF bit to a ‘0’.

In Mode 1 and 2, all receive buffers share RXBIE,

RXBIF and RXBIP in PIE3, PIR3 and IPR3, respec-

tively. Bits RXBnIE, RXBnIF and RXBnIP are not used.

Individual receive buffer interrupts can be controlled by

the TXBIE and BIE0 registers. In Mode 1, when a

shared receive interrupt occurs, user firmware must

poll the RXFUL bit of each receive buffer to detect the

source of interrupt. In Mode 2, a receive interrupt

indicates that the new message is loaded into FIFO.

FIFO can be read by using FIFO Pointer bits, FP.

TABLE 23-5:

VALUES FOR ICODE<3:1>

23.15.4

MESSAGE ERROR INTERRUPT

When an error occurs during transmission or reception

of a message, the message error flag, IRXIF, will be set

and if the IRXIE bit is set, an interrupt will be generated.

This is intended to be used to facilitate baud rate

determination when used in conjunction with Listen

Only mode.

ICODE

<2:0>

Interrupt

Boolean Expression

000

None

ERR•WAK•TX0•TX1•TX2•RX0•RX1

001

Error

ERR

010

TXB2

ERR•TX0•TX1•TX2

011

TXB1

ERR•TX0•TX1

100

TXB0

ERR•TX0

101

RXB1

ERR•TX0•TX1•TX2•RX0•RX1

110

RXB0

ERR•TX0•TX1•TX2•RX0

111

Wake on

Interrupt

ERR•TX0•TX1•TX2•RX0•RX1•WAK

Legend:

ERR = ERRIF * ERRIE

RX0 = RXB0IF * RXB0IE

TX0 = TXB0IF * TXB0IE

RX1 = RXB1IF * RXB1IE

TX1 = TXB1IF * TXB1IE

WAK = WAKIF * WAKIE

TX2 = TXB2IF * TXB2IE

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