PIC18F4680ISPQTP datasheet(258/482 Pages) MICROCHIP

258 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 256

Preliminary

19.7

Use of the CCP1 Trigger

An A/D conversion can be started by the “special event

trigger” of the ECCP1 module. This requires that the

ECCP1M3:ECCP1M0

bits

(ECCP1CON<3:0>)

programmed as ‘1011’ and that the A/D module is

enabled (ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D acquisition

and conversion and the Timer1 (or Timer3) counter will

be reset to zero. Timer1 (or Timer3) is reset to automat-

ically repeat the A/D acquisition period with minimal

software overhead (moving ADRESH/ADRESL to the

desired

location).

The

appropriate

analog

input

channel must be selected and the minimum acquisition

period is either timed by the user, or an appropriate

TACQ time selected before the “special event trigger”

sets the GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), the

“special event trigger” will be ignored by the A/D

module, but will still reset the Timer1 (or Timer3)

counter.

TABLE 19-2:

REGISTERS ASSOCIATED WITH A/D OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

IPR2

OSCFIP

CMIP(5)

—

EEIP

BCLIP

HLVDIP

TMR3IP

ECCP1IP(5)

PIR2

OSCFIF

CMIF(5)

—

EEIF

BCLIF

HLVDIF

TMR3IF

ECCP1IF(5)

PIE2

OSCFIE

CMIE(5)

—

EEIE

BCLIE

HLVDIE

TMR3IE

ECCP1IE(5)

ADRESH

A/D Result Register High Byte

ADRESL

A/D Result Register Low Byte

ADCON0

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

ADCON2

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

PORTA

RA7(2)

RA6(2)

RA5

RA4

RA3

RA2

RA1

RA0

TRISA

TRISA7(2) TRISA6(2) PORTA Data Direction Register

PORTB

Read PORTB pins, Write LATB Latch

TRISB

PORTB Data Direction Register

LATB

PORTB Output Data Latch

PORTE(4)

—

—RE3(3)

Read PORTE pins, Write LATE(1)

TRISE(4)

IBF

OBF

IBOV

PSPMODE

—

PORTE Data Direction

LATE(4)

—

LATE2

LATE1

LATE0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1:

These bits are unimplemented on PIC18F2X8X devices; always maintain these bits clear.

These pins may be configured as port pins depending on the oscillator mode selected.

RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.

These registers are not implemented on PIC18F2X8X devices.

These bits are available on PIC18F4X8X and reserved on PIC18F2X8X devices.

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