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PIC18F4680ISPQTP bảng dữ liệu(PDF) 215 Page - Microchip Technology

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Giải thích chi tiết về linh kiện  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN??Technology, 10-Bit A/D and nanoWatt Technology
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© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 213
PIC18F2585/2680/4585/4680
17.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3
demonstrates
clock
rates
based
on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 17-3:
I2C™ CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO
FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FCY
FCY*2
BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz
20 MHz
19h
400 kHz(1)
10 MHz
20 MHz
20h
312.5 kHz
10 MHz
20 MHz
64h
100 kHz
4 MHz
8 MHz
0Ah
400 kHz(1)
4 MHz
8 MHz
0Dh
308 kHz
4 MHz
8 MHz
28h
100 kHz
1 MHz
2 MHz
03h
333 kHz(1)
1 MHz
2 MHz
0Ah
100 kHz
1 MHz
2 MHz
00h
1 MHz(1)
Note 1:
The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.



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