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PIC18F4550ESOSQTP bảng dữ liệu(PDF) 400 Page - Microchip Technology

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Giải thích chi tiết về linh kiện  28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
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PIC18F4550ESOSQTP bảng dữ liệu(HTML) 400 Page - Microchip Technology

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PIC18F2455/2550/4455/4550
DS39632D-page 398
Preliminary
© 2007 Microchip Technology Inc.
TABLE 28-29: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
PIC18FXXXX
0.7
25.0(1)
μsTOSC based, VREF ≥ 3.0V
PIC18LFXXXX
1.4
25.0(1)
μsVDD = 2.0V,
TOSC based, VREF full range
PIC18FXXXX
TBD
1
μs
A/D RC mode
PIC18LFXXXX
TBD
3
μsVDD = 2.0V,
A/D RC mode
131
TCNV
Conversion Time
(not including acquisition time)(2)
11
12
TAD
132
TACQ
Acquisition Time(3)
1.4
TBD
—
—
μs
μs
-40
°C to +85°C
0
°C ≤ to ≤ +85°C
135
TSWC
Switching Time from Convert
→ Sample
—
(Note 4)
137
TDIS
Discharge Time
0.2
—
μs
Legend: TBD = To Be Determined
Note 1:
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2:
ADRES registers may be read on the following TCY cycle.
3:
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50
Ω.
4:
On the following cycle of the device clock.



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