PIC18F4550ESOSQTP datasheet(232/430 Pages) MICROCHIP

232 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 230

Preliminary

19.4.12

ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge

Sequence

Enable

bit,

ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into an inactive state

(Figure 19-25).

19.4.12.1

WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

19.4.13

STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Enable bit, PEN

(SSPCON2<2>). At the end of a receive/transmit, the

SCL line is held low after the falling edge of the ninth

clock. When the PEN bit is set, the master will assert

the SDA line low. When the SDA line is sampled low,

the Baud Rate Generator is reloaded and counts down

to ‘0’. When the Baud Rate Generator times out, the

SCL pin will be brought high and one TBRG (Baud Rate

Generator rollover count) later, the SDA pin will be

deasserted. When the SDA pin is sampled high while

SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG

later, the PEN bit is cleared and the SSPIF bit is set

(Figure 19-26).

19.4.13.1

WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 19-25:

ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 19-26:

STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

Set SSPIF at the

Acknowledge sequence starts here,

write to SSPCON2

ACKEN automatically cleared

Cleared in

TBRG

end of receive

ACKEN = 1, ACKDT = 0

SSPIF

software

Set SSPIF at the end

of Acknowledge sequence

Cleared in

software

ACK

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2,

set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

ninth clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

TBRG

to setup Stop condition

ACK

TBRG

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

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