PIC18F4550ESOSQTP datasheet(207/430 Pages) MICROCHIP

207 / 430 page

Preliminary

DS39632D-page 205

PIC18F2455/2550/4455/4550

SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE)

R/W-0

GCEN

ACKSTAT

ACKDT(1)

ACKEN(2)

RCEN(2)

PEN(2)

RSEN(2)

SEN(2)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GCEN: General Call Enable bit (Slave mode only)

Unused in Master mode.

bit 6

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

= Acknowledge was not received from slave

= Acknowledge was received from slave

bit 5

ACKDT: Acknowledge Data bit (Master Receive mode only)(1)

= Not Acknowledge

= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit(2)

= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically

cleared by hardware.

= Acknowledge sequence Idle

bit 3

RCEN: Receive Enable bit (Master Receive mode only)(2)

= Enables Receive mode for I2C

= Receive Idle

bit 2

PEN: Stop Condition Enable bit(2)

= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

= Stop condition Idle

bit 1

RSEN: Repeated Start Condition Enable bit(2)

= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

= Repeated Start condition Idle

bit 0

SEN: Start Condition Enable/Stretch Enable bit(2)

= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

= Start condition Idle

Note 1:

Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or

writes to the SSPBUF are disabled).

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