16F87 datasheet(105/228 Pages) MICROCHIP

105 / 228 page

 2005 Microchip Technology Inc.

DS30487C-page 103

PIC16F87/88

When setting up an asynchronous transmission, follow

these steps:

Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH (Section 11.1 “AUSART Baud

Rate Generator (BRG)”).

Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

If interrupts are desired, then set enable bit

TXIE.

If 9-bit transmission is desired, then set transmit

bit TX9.

Enable the transmission by setting bit TXEN

which will also set bit TXIF.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Load data to the TXREG register (starts

transmission).

If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

FIGURE 11-2:

ASYNCHRONOUS MASTER TRANSMISSION

FIGURE 11-3:

ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)

TABLE 11-7:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF(1)

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

-000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

19h

TXREG

AUSART Transmit Data Register

0000 0000

8Ch

PIE1

—

ADIE(1)

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

-000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Note

This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.

Word 1

Stop Bit

Word 1

Transmit Shift Reg

Start Bit

Bit 0

Bit 1

Bit 7/8

Write to TXREG

BRG Output

(Shift Clock)

RB5/SS/TX/CK pin

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

RB5/SS/TX/CK pin

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Word 2

Word 1

Word 2

Start Bit

Stop Bit

Start Bit

Transmit Shift Reg.

Word 1

Word 2

Bit 0

Bit 1

Bit 7/8

Bit 0

Note:

This timing diagram shows two consecutive transmissions.

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