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PIC18F4550ESOSQTP bảng dữ liệu(PDF) 187 Page - Microchip Technology

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Giải thích chi tiết về linh kiện  28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollerswith nanoWatt Technology
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© 2009 Microchip Technology Inc.
DS39632E-page 185
PIC18F2455/2550/4455/4550
17.5.4
USB ERROR INTERRUPT ENABLE
REGISTER (UEIE)
The
USB
Error
Interrupt
Enable
register
(Register 17-10) contains the enable bits for each of
the USB error interrupt sources. Setting any of these
bits will enable the respective error interrupt source in
the UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.
As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the micro-
controller’s interrupt logic. The flag bits are still set by
their interrupt conditions, allowing them to be polled
and serviced without actually generating an interrupt.
REGISTER 17-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BTSEE
—
—
BTOEE
DFN8EE
CRC16EE
CRC5EE
PIDEE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BTSEE: Bit Stuff Error Interrupt Enable bit
1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 4
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3
DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2
CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1
CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0
PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled



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