PIC18F2680ISPQTP datasheet(467/482 Pages) MICROCHIP

467 / 482 page

Preliminary

DS39625C-page 465

PIC18F2585/2680/4585/4680

INDEX

A/D ................................................................................... 247

Acquisition Requirements ........................................ 252

ADCON0 Register .................................................... 247

ADCON1 Register .................................................... 247

ADCON2 Register .................................................... 247

ADRESH Register ............................................ 247, 250

ADRESL Register .................................................... 247

Analog Port Pins, Configuring .................................. 254

Associated Registers ............................................... 256

Automatic Acquisition Time ...................................... 253

Configuring the Module ............................................ 251

Conversion Clock (TAD) ........................................... 253

Conversion Status (GO/DONE Bit) .......................... 250

Conversions ............................................................. 255

Converter Characteristics ........................................ 449

Converter Interrupt, Configuring .............................. 251

Operation in Power Managed Modes ...................... 254

Special Event Trigger (ECCP1) ....................... 174, 256

Use of the CCP1 Trigger .......................................... 256

Absolute Maximum Ratings ............................................. 415

AC (Timing) Characteristics ............................................. 431

Load Conditions for Device

Timing Specifications ....................................... 432

Parameter Symbology ............................................. 431

Temperature and Voltage Specifications ................. 432

Timing Conditions .................................................... 432

Access Bank ...................................................................... 69

Mapping with Indexed Literal Offset Mode ................. 93

ACKSTAT ........................................................................ 217

ACKSTAT Status Flag ..................................................... 217

ADCON0 Register ............................................................ 247

GO/DONE Bit ........................................................... 250

ADCON1 Register ............................................................ 247

ADCON2 Register ............................................................ 247

ADDFSR .......................................................................... 404

ADDLW ............................................................................ 367

ADDULNK ........................................................................ 404

ADDWF ............................................................................ 367

ADDWFC ......................................................................... 368

ADRESH Register ............................................................ 247

ADRESL Register .................................................... 247, 250

Analog-to-Digital Converter.

See A/D.

and BSR ............................................................................. 93

ANDLW ............................................................................ 368

ANDWF ............................................................................ 369

Assembler

MPASM Assembler .................................................. 412

Auto-Wake-up on Sync Break Character ......................... 240

Bank Select Register (BSR) ............................................... 67

Baud Rate Generator ....................................................... 213

Baud Rate Generator (BRG) ............................................ 231

BC .................................................................................... 369

BCF .................................................................................. 370

BF .................................................................................... 217

BF Status Flag ................................................................. 217

Bit Timing Configuration Registers

BRGCON1 ............................................................... 338

BRGCON2 ............................................................... 338

BRGCON3 ............................................................... 338

Block Diagrams

A/D ........................................................................... 250

Analog Input Model .................................................. 251

Baud Rate Generator .............................................. 213

CAN Buffers and Protocol Engine ........................... 274

Capture Mode Operation ......................................... 166

Comparator Analog Input Model .............................. 261

Comparator I/O Operating Modes ........................... 258

Comparator Output .................................................. 260

Comparator Voltage Reference ............................... 264

Compare Mode Operation ....................................... 167

Device Clock .............................................................. 28

Enhanced PWM ....................................................... 175

EUSART Receive .................................................... 238

EUSART Transmit ................................................... 236

External Power-on Reset Circuit

(Slow VDD Power-up) ........................................ 43

Fail-Safe Clock Monitor ........................................... 355

Generic I/O Port Operation ...................................... 129

High/Low-Voltage Detect with External Input .......... 268

MSSP (I2C Master Mode) ........................................ 211

MSSP (I2C Mode) .................................................... 196

MSSP (SPI Mode) ................................................... 187

On-Chip Reset Circuit ................................................ 41

PIC18F2585/2680 ..................................................... 10

PIC18F4585/4680 ..................................................... 11

PLL (HS Mode) .......................................................... 25

PORTD and PORTE (Parallel Slave Port) ............... 144

PWM Operation (Simplified) .................................... 169

Reads from Flash Program Memory ......................... 99

Single Comparator ................................................... 259

Table Read Operation ............................................... 95

Table Write Operation ............................................... 96

Table Writes to Flash Program Memory .................. 101

Timer0 in 16-Bit Mode ............................................. 148

Timer0 in 8-Bit Mode ............................................... 148

Timer1 ..................................................................... 152

Timer1 (16-Bit Read/Write Mode) ............................ 152

Timer2 ..................................................................... 158

Timer3 ..................................................................... 160

Timer3 (16-Bit Read/Write Mode) ............................ 160

Voltage Reference Output Buffer Example ............. 265

Watchdog Timer ...................................................... 352

BN .................................................................................... 370

BNC ................................................................................. 371

BNN ................................................................................. 371

BNOV .............................................................................. 372

BNZ ................................................................................. 372

BOR.

See Brown-out Reset.

BOV ................................................................................. 375

BRA ................................................................................. 373

BRG.

See Baud Rate Generator.

Brown-out Reset (BOR) ..................................................... 44

Detecting ................................................................... 44

Disabling in Sleep mode ............................................ 44

Software Enabled ...................................................... 44

BSF .................................................................................. 373

BTFSC ............................................................................. 374

BTFSS ............................................................................. 374

BTG ................................................................................. 375

BZ .................................................................................... 376

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