PIC18F2680ISPQTP datasheet(333/482 Pages) MICROCHIP

333 / 482 page

Preliminary

DS39625C-page 331

PIC18F2585/2680/4585/4680

In Mode 1 and 2, there are an additional 10 acceptance

filters, RXF6-RXF15, creating a total of 16 available

filters. RXF15 can be used either as an acceptance

filter or acceptance mask register. Each of these

acceptance filters can be individually enabled or

disabled by setting or clearing the RXFENn bit in the

RXFCONn register. Any of these 16 acceptance filters

can be dynamically associated with any of the receive

buffers. Actual association is made by setting appropri-

ate bits in the RXFBCONn register. Each RXFBCONn

be used to associate a specific filter to any of available

receive buffers. User firmware may associate more

than one filter to any one specific receive buffer.

In addition to dynamic filter to buffer association, in

Mode 1 and 2, each filter can also be dynamically asso-

ciated to available acceptance mask registers. The

FILn_m bits in the MSELn register can be used to link

a specific acceptance filter to an acceptance mask reg-

ister. As with filter to buffer association, one can also

associate more than one mask to a specific acceptance

filter.

When a filter matches and a message is loaded into the

receive buffer, the filter number that enabled the mes-

sage reception is loaded into the FILHIT bit(s). In

Mode 0 for RXB1, the RXB1CON register contains the

FILHIT<2:0> bits. They are coded as follows:

• 101 = Acceptance Filter 5 (RXF5)

• 100 = Acceptance Filter 4 (RXF4)

• 011 = Acceptance Filter 3 (RXF3)

• 010 = Acceptance Filter 2 (RXF2)

• 001 = Acceptance Filter 1 (RXF1)

• 000 = Acceptance Filter 0 (RXF0)

The coding of the RXB0DBEN bit enables these three

bits to be used similarly to the FILHIT bits and to

distinguish a hit on filter RXF0 and RXF1, in either

RXB0 or after a rollover into RXB1.

• 111 = Acceptance Filter 1 (RXF1)

• 110 = Acceptance Filter 0 (RXF0)

• 001 = Acceptance Filter 1 (RXF1)

• 000 = Acceptance Filter 0 (RXF0)

If the RXB0DBEN bit is clear, there are six codes

corresponding to the six filters. If the RXB0DBEN bit is

set, there are six codes corresponding to the six filters,

plus two additional codes corresponding to RXF0 and

RXF1 filters, that rollover into RXB1.

In Mode 1 and 2, each buffer control register contains

5 bits of filter hit bits (FILHIT<4:0>). A binary value of ‘0’

indicates a hit from RXF0 and 15 indicates RXF15.

If more than one acceptance filter matches, the FILHIT

bits will encode the binary value of the lowest num-

bered filter that matched. In other words, if filter RXF2

and filter RXF4 match, FILHIT will be loaded with the

value for RXF2. This essentially prioritizes the

acceptance filters with a lower number filter having

higher priority. Messages are compared to filters in

ascending order of filter number.

The mask and filter registers can only be modified

when the PIC18F2585/2680/4585/4680 devices are in

Configuration mode.

FIGURE 23-3:

MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

Note:

‘000’ and ‘001’ can only occur if the

RXB0DBEN bit is set in the RXB0CON

rollover into RXB1.

Acceptance Filter Register

Acceptance Mask Register

RxRqst

Message Assembly Buffer

RXFn0

RXFn1

RXFnn

RXMn0

RXMn1

RXMnn

Identifier

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