18F8680 datasheet(167/496 Pages) MICROCHIP

167 / 496 page

 2004 Microchip Technology Inc.

DS30491C-page 165

PIC18F6585/8585/6680/8680

14.1

Timer3 Operation

Timer3 can operate in one of these modes:

•As a timer

• As a synchronous counter

• As an asynchronous counter

The operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>).

When TMR3CS = 0, Timer3 increments every instruc-

tion cycle. When TMR3CS = 1, Timer3 increments on

every rising edge of the Timer1 external clock input or

the Timer1 oscillator if enabled.

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored and the pins are read as ‘0’.

Timer3 also has an internal “Reset input”. This Reset

can be generated by the CCP module (Section 14.0

“Timer3 Module”).

FIGURE 14-1:

TIMER3 BLOCK DIAGRAM

FIGURE 14-2:

TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

TMR3H

TMR3L

T1OSC

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Sleep Input

T1OSCEN

Enable

Oscillator(1)

TMR3IF

Overflow

Interrupt

FOSC/4

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T1OSO/

T1OSI

Flag bit

(3)

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

T13CKI

CLR

CCP Special Trigger

T3CCPx

Timer3

TMR3L

T1OSC

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Sleep Input

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T1OSO/

T1OSI

TMR3

T13CKI

CLR

CCP Special Trigger

T3CCPx

To Timer1 Clock Input

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

High Byte

Data Bus<7:0>

TMR3H

Read TMR3L

Write TMR3L

Set TMR3IF Flag bit

on Overflow

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