DM3725CBC datasheet(203/280 Pages) TI

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DM3730, DM3725

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SPRS685D

– AUGUST 2010 – REVISED JULY 2011

6.5.2

Display Subsystem (DSS)

NOTE

For more information, see Display Subsystem chapter of the AM/DM37x Multimedia Device

Technical Reference Manual (literature number SPRUGN4).

The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or

internal (SRAM) memory on an LCD panel or a TV set. The display subsystem integrates the following

elements:

•

Display controller (DISPC) module

•

Remote frame buffer interface (RFBI) module

•

NTSC/PAL video encoder

•

LCD display with:

– Parallel Interface

The two display supports can be active at the same time.

6.5.2.1

DSS

—Parallel Interface

In parallel interface, the paths of the display subsystem modules are the display controller and the RFBI.

The display controller has two I/O pad modes and could be in the following configuration:

•

Bypass mode (RFBI disabled), which implements the MIPI DPI protocol

•

RFBI mode (RFBI enabled), which implements MIPI DBI 2.0 type B protocol

For more information about MIPI DPI and MIPI DBI protocols, see the DSS chapter in the AM/DM37x

Multimedia Device Technical Reference Manual (literature number SPRUGN4).

6.5.2.1.1 DSS

—Parallel Interface—Bypass Mode

Two types of LCD panel are supported:

•

Thin film transistor (TFT) or active matrix technology

•

Supertwisted nematic (STN) or passive matrix technology

Both configurations are discussed in the following paragraphs.

6.5.2.1.2 DSS

—Parallel Interface—Bypass Mode—TFT Mode

Table 6-36 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-30).

Table 6-35. DSS Timing Conditions

—TFT Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Output Condition

CLOAD

Output load capacitance(1)

(1) Buffer strength configuration: LB0 = 1

Table 6-36. DSS Switching Characteristics

—TFT Mode(4)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

DL0

td(pclkA-hsync)

Delay time, output pixel clock dss_pclk active edge to

–4.215

4.215

–4.658

4.658

output horizontal synchronization dss_hsync transition

DL1

td(pclkA-vsync)

Delay time, output pixel clock dss_pclk active edge to

–4.215

4.215

–4.658

4.658

output vertical synchronization dss_vsync transition

Timing Requirements and Switching Characteristics

203

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