DM3725CBC datasheet(124/280 Pages) TI

124 / 280 page

DM3730, DM3725

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

www.ti.com

Table 3-5. DC Electrical Characteristics (continued)

PARAMETER

MIN

NOM

MAX

UNIT

Input Capacitance and Input Transition Time

sys_xtalin pin (CBP Ball(19): AE17)

CIN

Input capacitance

1.00

1.15

1.35

tTIN

(2)

Input transition time (rise time, tRIN or fall time, tFIN

evaluated between 10% and 90% at PAD)

JTAG interface (CBP Balls(19): AA17 / AA13 / AA12 / AA18 / AA20 / AA19 / AA11 / AA10)

CIN

Input capacitance

2.20

tTIN

(2)

Input transition time (rise time, tRIN or fall time, tFIN

evaluated between 10% and 90% at PAD)

Otherwise

CIN

Input capacitance

1.15

tTIN

(2)

Input transition time (rise time, tRIN or fall time, tFIN

evaluated between 10% and 90% at PAD)

Output Capacitance Load and Output Transition Time

sys_32k, sys_clkreq, sys_off_mode, sys_clkout1, sys_nirq, uart3_cts_rctx, uart3_rts_sd, uart3_rx_irrx, uart3_tx_irtx, hdq_sio

(CBP Balls(19): R27 / AE25 / AF25 / AF22 / AG25 / AF26 / H18 / H19 / H20 / H21 / J25)

tTOUT

Output transition time (rise time, tROUT or

DS[1:0] = 00(3)

1(15)

15(16)

fall time, tFOUT evaluated between 10% and

90% at PAD)

CTOUT

Output load

tTOUT

Output transition time (rise time, tROUT or

DS[1:0] = 10(3)

0.4(15)

5(16)

fall time, tFOUT evaluated between 10% and

90% at PAD)

CTOUT

Output load

tTOUT

Output transition time (rise time, tROUT or

DS[1:0] = 01(3)

0.6(15)

7(16)

fall time, tFOUT evaluated between 10% and

90% at PAD)

CTOUT

Output load

CAM, HSUSB0, MMC2, UART1, UART2, McBSP, McSPI, ETK Interfaces, sys_clkout2 (CBP Ball(19): AE22)

tTOUT

Output transition time (rise time, tROUT or fall time, tFOUT

1.5

evaluated between 10% and 90% at PAD)

CTOUT

Output load

Otherwise

tTOUT

Output transition time (rise time, tROUT or fall time, tFOUT

0.6

2.4(17)

evaluated between 10% and 90% at PAD)

CTOUT

Output load

Hysteresis

sys_xtalin pin (CBP Ball(19): AE17)

VHYS

(1)

Hysteresis voltage at an input

0.25

hsusb0_clk (CBP Ball(19): T28)

VHYS

(1)

Hysteresis voltage at an input

0.07

Otherwise

VHYS

(1)

Hysteresis voltage at an input

0.15

(1) Vhys is the magnitude of the difference between the positive-going threshold voltage VT+ and the negative-going threshold voltage VT–.

Some receivers, but not all, are designed for hysteresis. Vhys applies only to those that are.

(2) The tIN (tRIN and tFIN also) value is the recommended condition. The tIN (tRIN and tFIN also) mismatch causes additional delay time inside

the device then leads to ac timing invalidation in this DM.

The tIN (tRIN and tFIN also) mismatch does not necessarily mean functional failure. This global value may be overridden on a per interface

basis if another value is explicitly defined for that interface in the Timing Requirements and Switching Characteristics chapter of the data

manual.

(3) For a full description of the DS0 load compensation register configuration, see the description of the CONTROL_PROG_IO1

configuration registers in System Control Module / Programming Model / Feature Settings / SDRC I/O Drive Strength Selection section

of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).

124

Electrical Characteristics

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