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DSPIC33FJ06GS101TE/ML bảng dữ liệu(PDF) 141 Page - Microchip Technology |
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DSPIC33FJ06GS101TE/ML bảng dữ liệu(HTML) 141 Page - Microchip Technology |
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141 / 346 page ![]() © 2009 Microchip Technology Inc. Preliminary DS70318D-page 139 dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307) in the “dsPIC33F Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. |
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