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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AM3703CUS bảng dữ liệu(PDF) 141 Page - Texas Instruments |
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AM3703CUS bảng dữ liệu(HTML) 141 Page - Texas Instruments |
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141 / 280 page  AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 4.3.1 DPLL Characteristics Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating conditions. Table 4-14. DPLL1 - DPLL3 - DPLL5 Characteristics NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS vdda_dplls_dll Supply voltage for DPLLs (MPUand 1.71 1.8 1.91 V Core) and DLL vdda_dpll_per Supply voltage for DPLL 1.71 1.8 1.91 V (Peripherals) finput CLKINP Input frequency 0.032 52 MHz FINP finternal Internal reference frequency 0.032 52 MHz REFCLK fCLKINPHIF CLKINPHIF Input frequency 10 1000 MHz FINPHIF fCLKINPULOW CLKINPULOW Input frequency 0.001 800 MHz fCLKOUT CLKOUT output frequency 10(1) 1000(2) MHz [M / (N + 1)] * FINP * [1 / M2] fCLKOUTx2 CLKOUTx2 output frequency 20(1) 2000(2) MHz 2 * [M / (N + 1)] * FINP * [1 / M2] fCLKOUTHIF CLKOUTHIF output frequency 10(3) 1000(4) MHz FINPHIF / M3 20(3) 2000(4) 2 * [M / (N + 1)] * FINP * [1 / M3] fDCOCLKLDO DCOCLKLDO output frequency 20 2000 MHz 2 * [M / (N + 1)] * FINP tlock Frequency lock time 1.9 + μs 350*REFCLK plock Phase lock time 1.9 + μs 500*REFCLK trelock-L Relock time —Frequency lock(5) (Low 1.9 + 70*REFCLK μs DPLL in low-power mode: power bypass) lowcurrstdby = 1 prelock-L Relock time —Phase lock(5) (Low 1.9 + μs DPLL in low-power mode: power bypass) 120*REFCLK lowcurrstdby = 1 trelock-F Relock time —Frequency lock(5) (Fast 0.05 + μs DPLL in normal mode: relock bypass) 70*REFCLK lowcurrstdby = 0 prelock-F Relock time —Phase lock(5) (Fast 0.05 + μs DPLL in normal mode: relock bypass) 120*REFCLK lowcurrstdby = 0 (1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1. For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2. (2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1. (3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down by factor of M3. (4) The maximum frequency on CLKOUTHIF is assuming M3 = 1. (5) Relock time assumes typical operating conditions, 10 °C maximum temperature drift. Table 4-15. DPLL4 Characteristics NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS vdda_dpll_per Supply voltage for DPLL (peripherals) 1.71 1.8 1.91 V finput CLKINP input clock frequency 0.5 60 MHz FINP finternal REFCLK internal reference frequency 0.5 2.5 MHz REFCLK fCLKINPULOW CLKINPULOW bypass input 0.001 800 MHz frequency fCLKOUT CLKOUT output clock frequency 10(1) 2000(2) MHz [M / (N + 1)] * FINP * [1 / M2] fDCOCLKLDO Internal oscillator (DCO) output clock 500 2000 MHz [M / (N + 1)] * FINP frequency tlock Frequency lock time 350*REFCLK μs plock Phase lock time 500*REFCLK μs trelock-L Relock time —Frequency lock(3) (Low 7.5 + μs DPLL in low-power mode: power bypass) 30*REFCLKs lowcurrstdby = 1 Copyright © 2010–2011, Texas Instruments Incorporated Clock Specifications 141 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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