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PIC18F2610I/SOSQTP bảng dữ liệu(PDF) 171 Page - Microchip Technology

tên linh kiện PIC18F2610I/SOSQTP
Giải thích chi tiết về linh kiện  28/40/44-Pin Flash Microcontrollers
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nhà sản xuất  MICROCHIP [Microchip Technology]
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© 2009 Microchip Technology Inc.
DS39636D-page 173
PIC18F2X1X/4X1X
16.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 16-12).
FIGURE 16-12:
CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX – 1
DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock



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