PIC16F1825T-ESS datasheet(140/448 Pages) MICROCHIP

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140 / 448 page

PIC16(L)F1825/1829

DS41440C-page 140

 2010-2012 Microchip Technology Inc.

FIGURE 13-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)

13.6

Interrupt-on-Change Registers

RAx

IOCANx

IOCAPx

Q4Q1

Data Bus =

0 or 1

Write IOCAFx

IOCIE

To Data Bus

IOCAFx

Edge

Detect

IOC interrupt

to CPU core

From all other

IOCAFx individual

pin detectors

Q4Q1

IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

U-0

R/W-0/0

—

IOCAP5

IOCAP4

IOCAP3

IOCAP2

IOCAP1

IOCAP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-6

Unimplemented: Read as ‘0’

bit 5-0

IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1 = Interrupt-on-change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will

be set upon detecting an edge.

0 = Interrupt-on-change disabled for the associated pin.

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