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OMAP3530ECBBA bảng dữ liệu(PDF) 235 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  OMAP3530/25 Applications Processor: OMAP 3 Architecture
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OMAP3530ECBBA bảng dữ liệu(HTML) 235 Page - Texas Instruments

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OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
HSSD3/SD3
tsu(CMDV-CLKIH)
Setup time, mmc2_cmd valid before
1198.4
1198.4
ns
mmc2_clk rising clock edge
HSSD4/SD4
tsu(CLKIH-CMDIV)
Hold time, mmc2_cmd valid after
1249.2
1249.2
ns
mmc2_clk rising clock edge
MMC/SD/SDIO Interface 3
HSSD3/SD3
tsu(CMDV-CLKIH)
Setup time, mmc3_cmd valid before
1198.4
1198.4
ns
mmc3_clk rising clock edge
HSSD4/SD4
tsu(CLKIH-CMDIV)
Hold time, mmc3_cmd valid after
1249.2
1249.2
ns
mmc3_clk rising clock edge
Table 6-119. MMC/SD/SDIO Switching Characteristics – SD Identification Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
SD Identification Mode
1 /
1/tc(clk)
Frequency(2), mmcx_ clk (3)
0.4
0.4
MHz
(HSSD1/SD1
)
HSSD2/SD2
tW(clkH)
Typical pulse duration, output clk high
X(4)*PO(5)
X(4)*PO(5)
ns
HSSD2/SD2
tW(clkL)
Typical pulse duration, output clk low
Y(6)*PO(5)
Y(6)*PO(5)
ns
tdc(clk)
Duty cycle error, output clk
125
125
ns
tj(clk)
Jitter standard deviation(7), output clk
200
200
ps
MMC/SD/SDIO Interface 1 (1.8 V IO)
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
HSSD5/SD5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
6.3
2492.7
6.3
2492.7
ns
mmc1_cmd transition
MMC/SD/SDIO Interface 1 (3.0 V IO)
tc(clk)
Rise time, output clk
10
0
ns
tW(clkH)
Fall time, output clk
10
0
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
HSSD5/SD5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
6.3
2492.7
6.3
2492.7
ns
mmc1_cmd transition
MMC/SD/SDIO Interface 2
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
HSSD5/SD5
td(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to
6.3
2492.7
6.3
2492.7
ns
mmc2_cmd transition
MMC/SD/SDIO Interface 3
tc(clk)
Rise time, output clk
10
10
ns
(1)
Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).
(2)
Related with the output clk maximum and minimum frequencies programmable in I/F module.
(3)
In mmcx_clk, 'x' is equal to 1, 2, or 3.
(4)
The X parameter is defined as shown in Table 6-120.
(5)
PO = output clk period in ns.
(6)
The Y parameter is defined as shown in Table 6-121.
(7)
The jitter probability density can be approximated by a Gaussian function.
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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