HT85F2270 datasheet(209/226 Pages) HOLTEK

209 / 226 page

Rev. 1.00

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

UART0 Multiprocessor Communication

As UART0 can receive 9 bits in Modes 2 and 3, it can be used for multiprocessor communication.

When the SM20 bit in the S0CON register is set, the received interrupt is generated only when the

9th received bit, the RB80 bit in the S0CON register, is high. Otherwise, no interrupt is generated

upon reception.

To utilise this feature for multiprocessor communication, the slave processors have their SM20 bit

set high. The master processor transmits the slave’s address, with the 9th bit set high, generating a

reception interrupt in all of the slaves. The slave processors’ software compares the received byte

with their network address. If there is a match, the addressed slave clears its SM20 flag and the rest

of the message is transmitted from the master with the 9th bit cleared to zero. The other slaves keep

their SM20 set high so that they ignore the rest of the message sent by the master. In this way, there

are reduced program overheads to distinguish the target slave MCU.

UART0 Baud Rate Setup

The UART0 operating Modes1 and 3, have a variable baud rate setup using the UART0 Baud rate

generator. The clock source can be selected to be either the Timer 1 overflow or the system clock,

decided by the BD bit in the SBRCON register. The baud rate generator can be controlled by the

S0RELH and S0RELL registers and the clock is the output of the prescaler, defined by the S0PRE0

and S0PRE1 bits. Operating Mode 0 has a fixed baud rate of fSYS/12 and operating Mode 2, has two

baud rates, SP0CLK/64 and SP0CLK/32, selected by the SMOD bit in the PCON register.

fSYS

10-bit Timer

S0RELH[1:0] S0RELL[7:0]

Timer 1

Overflow

S�OD

UART0

Baud Rate

SP0CLK

fSYS/4

fSYS

fSYS/6

fSYS/1�

S0PRE0

S0PRE1

�

�UX

fSYS/1�

S�[1:0]

01� 11

S�OD

Variable

÷� SP0CLK/�

÷�

÷16

SP0CLK/64

SP0CLK/��

UART0 Baud Rate Generator

The Variable baud rate, which is provided for Mode 1 and Mode 3, can be derived using the

following two equations, depending upon the BD bit condition.

BD=0 – Timer1 overflow clock source.

)

(

Rate

Overflow

Timer

Rate

Baud

SMOD

BD=1 – Register select clock Source.

)

(

])

[

(

CLK

Freq

REL

Rate

Baud

SMOD

−

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